1. Field of the Invention
The present invention relates to an interpolating A/D converter.
2. Description of Related Art
An A/D (Analog/Digital) converter that includes a plurality of comparators is generally used for converting an analog signal to a digital signal. In order to increase the resolution of signal conversion in such an A/D converter, a large number of amplifiers for driving comparators need to be placed in the previous stage of the comparators. As a result, a circuit overhead becomes larger. This raises problems such as a decrease in the yield of the A/D converter and a failure to reduce the cost of a semiconductor chip that incorporates the A/D converter.
To address such problems, a generally used technique is to reduce the number of amplifiers by interpolating output signals between adjacent amplifiers with use of an interpolation circuit, such as an interpolating A/D converter disclosed in Japanese Unexamined Patent Application Publication No. 2009-21667.
FIG. 16 is a block diagram showing a configuration of a typical interpolating A/D converter. Referring to FIG. 16, the interpolating A/D converter includes a reference voltage generation circuit 401, an analog signal input circuit 402, a preamplifier group 403, an interpolation circuit 404, and a comparator group 405.
In the reference voltage generation circuit 401, a resistor ladder 401a that includes 2n (n is an integer of one or greater) number of resistors 401b is connected between a maximum reference voltage VRT and a minimum reference voltage VRB. The reference voltage generation circuit 401 generates (2n+1) kinds of reference voltages Vr and outputs them to the preamplifier group 403. In FIG. 16, the respective reference voltages Vr are denoted by the reference symbols Vr−n to Vrn in order to distinguish among them.
The analog signal input circuit 402 outputs an analog signal AIN to the preamplifier group 403.
The preamplifier group 403 is made up of (2n+1) number of preamplifiers AMP4. In FIG. 16, the respective preamplifiers AMP4 are denoted by the reference symbols AMP4−n to AMP4n in order to distinguish among them. The preamplifiers AMP4 output amplified signals of the analog signal AIN and the reference voltages Vr to the interpolation circuit 404 and the comparator group 405.
The interpolation circuit 404 includes 8n number of resistors 404a. The interpolation circuit 404 interpolates output signals of the adjacent preamplifiers AMP4 and outputs interpolation signals to the comparator group 405.
The comparator group 405 includes (4n+1) number of comparators 405a. The comparator group 405 compares the signals output from the preamplifiers AMP4 with the interpolation signals output from the interpolation circuit 404 and outputs signals to an encoder (not shown) or the like.
In this configuration, it is assumed that a voltage of the analog signal AIN and the reference voltage Vr0 are equal in AMP40.
Next, a configuration of the preamplifier AMP4 is described. FIG. 17 is a block diagram showing a configuration of the preamplifier AMP4. Referring to FIG. 17, between a ground voltage GND and a power supply voltage VDD, a tail current source 43, a differential pair 41 composed of Nch (N-channel) transistors 41a and 41b, and load resistors 42a and 42b are connected sequentially from the side of the ground voltage GND.
A gate voltage VINP4 of the Nch transistor 41a is a voltage of the analog signal AIN. A gate voltage VINN4 of the Nch transistor 41b is the reference voltage Vr.
Further, a voltage between the Nch transistor 41a and the load resistor 42a is an output voltage VOUTN4. A voltage between the Nch transistor 41b and the load resistor 42b is an output voltage VOUTP4.
An operation of the preamplifier AMP4 is described hereinbelow. In the preamplifier AMP4, the differential pair 41 operates according to the gate voltages VINP4 and VINN4. A current I flows through the preamplifier AMP4. The current I divides into a current Ia that flows through the Nch transistor 41a and the load resistor 42a and a current Ib that flows through the Nch transistor 41b and the load resistor 42b. Thus, current I=Ia+Ib flows between the power supply voltage VDD and the ground voltage GND. The values of Ia and Ib are determined depending on a differential voltage ΔV4 (ΔV4=VINP4−VINN4; the same applies below).
Further, the tail current source 43 keeps the current I at a constant level. Thus, the same level of current flows through the respective preamplifiers AMP4n to AMP4−n.